The assembly processes utilized in the assembly of microelectronic package structures, such as package on package (PoP), various ball grid array (BGA) structures, and/or even die attach processes, for example, can be a fabrication challenge for electronic manufacturers. Surface mount technologies (SMT) that may be used to assemble PoP package structures may suffer yield loss due to solder joint opens and solder bridging failure mechanisms, particularly when packaged die/devices undergo reflow process during SMT assembly and/or any other attachment processes, such as thermal compression bonding, for example.